Guide to chip layout reverse engineering
In order to study chip logic you need two sort of chip images:
- High quality surface photo. It will be used mainly to restore metal layer. But also it can contain enough information to search for viases and polysilicon traces.
- High quality delayered photo, with metal layer melted out by acid. This photo is required to trace diffusion layer, which is usually hidden under metal wires.
Metal traces are used mainly for power supply and grounding. But sometimes it can be used as interconnections.
When polysilicon wire crossing n-type diffusion it forms transistor. Often polysilicon used as interconnection.
Vias is used to connect metal with poly/diffusion layers. Buried (hidden) contacts are used to connect poly with diffusion, without any additional poly->metal->diffusion vias.
Difference between NMOS and CMOS
NMOS using only single type of diffusion (n-type).
CMOS using both types of diffusion: n-type and p-type, reducing amount of additional inverters in chip logic (since p-type MOSFET is open when its base has low level)
Some 6502 tracing 😄
Part 1: prepare two layers
Part 2: trace layers
Part 2: Transistor schematics